Comparing Reliability/Redundancy Trade-offs of Von Neumann Based Multiplexing Architectures

Majority gates play an important role in defectand fault-tolerant circuit implementations for nanotechnologies due to their use in redundancy mechanisms such as TMR, CTMR etc. Therefore, providing reliable implementation of majority logic using some redundancy mechanism is extremely important. This problem was addressed by von Neumann in 1956, in the form of ”majority multiplexing” and since then several analytical probabilistic models have been proposed to analyze majority multiplexing circuits. However, such analytical approaches are extremely challenging combinatorially and error prone. Also the previous analyses did not distinguish between permanent faults at the gates and transient faults due to noisy interconnects or noise effects on gates. In this paper, we provide explicit fault models for transient and permanent errors at the gates and noise effects at the interconnects. We model majority multiplexing in a probabilistic system description language, and use probabilistic model checking to analyze the effects of our fault models on the different reliability/redundancy trade-offs for majority multiplexing configurations. We also draw parallels with another fundamental logic gate multiplexing technique, namely NAND multiplexing. VLSI designs at the nano-scale will utilize implementation fabrics prone to faults of permanent and transient nature, and the interconnects will be extensively affected by noise, hence a comparative study of NAND multiplexing vs. majority multiplexing is needed in case the designers are confronted with the choice to implement redundancy in either way to mitigate the effects of such faults. This paper provides models, methodologies and tools that can capture probabilistically quantified fault models and provide quick evaluation of the trade-offs.